vhdl-sphinx-domain

Getting started

  • Home page
    • Installation
    • Documentation
    • Usage
    • Examples
      • Autogenerated Entity documentation
      • Memory Map extracted from a comment block
    • How it works

API Reference

  • vhdl_sphinx_domain package
    • ansi module
    • doc_utils module
      • create_table_nodes()
      • create_wavedrom_reg_nodes()
      • make_lexed_vhdl_node()
      • make_vhdl_entity_table()
      • parse_comment_block()
      • parse_markdown_table()
      • parse_rest()
    • vhdl_domain module
      • vhdl_code_role()
      • VHDLDirective
        • VHDLDirective.__init__()
        • VHDLDirective.add_contents()
        • VHDLDirective.add_name()
        • VHDLDirective.add_target_and_index()
        • VHDLDirective.after_content()
        • VHDLDirective.assert_has_content()
        • VHDLDirective.before_content()
        • VHDLDirective.config
        • VHDLDirective.debug()
        • VHDLDirective.directive_error()
        • VHDLDirective.doc_field_types
        • VHDLDirective.domain
        • VHDLDirective.env
        • VHDLDirective.error()
        • VHDLDirective.final_argument_whitespace
        • VHDLDirective.get_field_type_map()
        • VHDLDirective.get_location()
        • VHDLDirective.get_signatures()
        • VHDLDirective.get_source_info()
        • VHDLDirective.handle_signature()
        • VHDLDirective.has_content
        • VHDLDirective.indexnode
        • VHDLDirective.indextemplate
        • VHDLDirective.info()
        • VHDLDirective.objtype
        • VHDLDirective.option_spec
        • VHDLDirective.optional_arguments
        • VHDLDirective.parse_content_to_nodes()
        • VHDLDirective.parse_inline()
        • VHDLDirective.parse_text_to_nodes()
        • VHDLDirective.required_arguments
        • VHDLDirective.run()
        • VHDLDirective.set_source_info()
        • VHDLDirective.severe()
        • VHDLDirective.transform_content()
        • VHDLDirective.warning()
      • VHDLDomain
        • VHDLDomain.__init__()
        • VHDLDomain.add_object_type()
        • VHDLDomain.check_consistency()
        • VHDLDomain.clear_doc()
        • VHDLDomain.dangling_warnings
        • VHDLDomain.data
        • VHDLDomain.data_version
        • VHDLDomain.directive()
        • VHDLDomain.directives
        • VHDLDomain.enumerable_nodes
        • VHDLDomain.get_enumerable_node_type()
        • VHDLDomain.get_full_qualified_name()
        • VHDLDomain.get_objects()
        • VHDLDomain.get_type_name()
        • VHDLDomain.indices
        • VHDLDomain.initial_data
        • VHDLDomain.label
        • VHDLDomain.merge_domaindata()
        • VHDLDomain.name
        • VHDLDomain.object_types
        • VHDLDomain.process_doc()
        • VHDLDomain.process_field_xref()
        • VHDLDomain.resolve_any_xref()
        • VHDLDomain.resolve_xref()
        • VHDLDomain.role()
        • VHDLDomain.roles
        • VHDLDomain.setup()
      • VHDLEntityDirective
        • VHDLEntityDirective.__init__()
        • VHDLEntityDirective.add_contents()
        • VHDLEntityDirective.add_name()
        • VHDLEntityDirective.add_target_and_index()
        • VHDLEntityDirective.after_content()
        • VHDLEntityDirective.assert_has_content()
        • VHDLEntityDirective.before_content()
        • VHDLEntityDirective.config
        • VHDLEntityDirective.debug()
        • VHDLEntityDirective.directive_error()
        • VHDLEntityDirective.doc_field_types
        • VHDLEntityDirective.domain
        • VHDLEntityDirective.env
        • VHDLEntityDirective.error()
        • VHDLEntityDirective.final_argument_whitespace
        • VHDLEntityDirective.get_field_type_map()
        • VHDLEntityDirective.get_location()
        • VHDLEntityDirective.get_signatures()
        • VHDLEntityDirective.get_source_info()
        • VHDLEntityDirective.handle_signature()
        • VHDLEntityDirective.has_content
        • VHDLEntityDirective.indexnode
        • VHDLEntityDirective.indextemplate
        • VHDLEntityDirective.info()
        • VHDLEntityDirective.objtype
        • VHDLEntityDirective.option_spec
        • VHDLEntityDirective.optional_arguments
        • VHDLEntityDirective.parse_content_to_nodes()
        • VHDLEntityDirective.parse_inline()
        • VHDLEntityDirective.parse_text_to_nodes()
        • VHDLEntityDirective.required_arguments
        • VHDLEntityDirective.run()
        • VHDLEntityDirective.set_source_info()
        • VHDLEntityDirective.severe()
        • VHDLEntityDirective.transform_content()
        • VHDLEntityDirective.warning()
      • VHDLIncludeDirective
        • VHDLIncludeDirective.__init__()
        • VHDLIncludeDirective.add_contents()
        • VHDLIncludeDirective.add_name()
        • VHDLIncludeDirective.add_target_and_index()
        • VHDLIncludeDirective.after_content()
        • VHDLIncludeDirective.assert_has_content()
        • VHDLIncludeDirective.before_content()
        • VHDLIncludeDirective.config
        • VHDLIncludeDirective.debug()
        • VHDLIncludeDirective.directive_error()
        • VHDLIncludeDirective.doc_field_types
        • VHDLIncludeDirective.domain
        • VHDLIncludeDirective.env
        • VHDLIncludeDirective.error()
        • VHDLIncludeDirective.final_argument_whitespace
        • VHDLIncludeDirective.get_field_type_map()
        • VHDLIncludeDirective.get_location()
        • VHDLIncludeDirective.get_signatures()
        • VHDLIncludeDirective.get_source_info()
        • VHDLIncludeDirective.handle_signature()
        • VHDLIncludeDirective.has_content
        • VHDLIncludeDirective.indexnode
        • VHDLIncludeDirective.indextemplate
        • VHDLIncludeDirective.info()
        • VHDLIncludeDirective.objtype
        • VHDLIncludeDirective.option_spec
        • VHDLIncludeDirective.optional_arguments
        • VHDLIncludeDirective.parse_content_to_nodes()
        • VHDLIncludeDirective.parse_inline()
        • VHDLIncludeDirective.parse_text_to_nodes()
        • VHDLIncludeDirective.required_arguments
        • VHDLIncludeDirective.run()
        • VHDLIncludeDirective.set_source_info()
        • VHDLIncludeDirective.severe()
        • VHDLIncludeDirective.transform_content()
        • VHDLIncludeDirective.warning()
      • VHDLParseDirective
        • VHDLParseDirective.__init__()
        • VHDLParseDirective.add_contents()
        • VHDLParseDirective.add_name()
        • VHDLParseDirective.add_target_and_index()
        • VHDLParseDirective.after_content()
        • VHDLParseDirective.assert_has_content()
        • VHDLParseDirective.before_content()
        • VHDLParseDirective.config
        • VHDLParseDirective.debug()
        • VHDLParseDirective.directive_error()
        • VHDLParseDirective.doc_field_types
        • VHDLParseDirective.domain
        • VHDLParseDirective.env
        • VHDLParseDirective.error()
        • VHDLParseDirective.final_argument_whitespace
        • VHDLParseDirective.get_field_type_map()
        • VHDLParseDirective.get_location()
        • VHDLParseDirective.get_signatures()
        • VHDLParseDirective.get_source_info()
        • VHDLParseDirective.handle_signature()
        • VHDLParseDirective.has_content
        • VHDLParseDirective.indexnode
        • VHDLParseDirective.indextemplate
        • VHDLParseDirective.info()
        • VHDLParseDirective.objtype
        • VHDLParseDirective.option_spec
        • VHDLParseDirective.optional_arguments
        • VHDLParseDirective.parse_content_to_nodes()
        • VHDLParseDirective.parse_inline()
        • VHDLParseDirective.parse_text_to_nodes()
        • VHDLParseDirective.required_arguments
        • VHDLParseDirective.run()
        • VHDLParseDirective.set_source_info()
        • VHDLParseDirective.severe()
        • VHDLParseDirective.transform_content()
        • VHDLParseDirective.warning()
      • VHDLXRefRole
        • VHDLXRefRole.__call__()
        • VHDLXRefRole.__init__()
        • VHDLXRefRole.config
        • VHDLXRefRole.content
        • VHDLXRefRole.create_non_xref_node()
        • VHDLXRefRole.create_xref_node()
        • VHDLXRefRole.disabled
        • VHDLXRefRole.env
        • VHDLXRefRole.explicit_title_re
        • VHDLXRefRole.get_location()
        • VHDLXRefRole.get_source_info()
        • VHDLXRefRole.has_explicit_title
        • VHDLXRefRole.inliner
        • VHDLXRefRole.innernodeclass
        • VHDLXRefRole.lineno
        • VHDLXRefRole.name
        • VHDLXRefRole.nodeclass
        • VHDLXRefRole.options
        • VHDLXRefRole.process_link()
        • VHDLXRefRole.rawtext
        • VHDLXRefRole.result_nodes()
        • VHDLXRefRole.run()
        • VHDLXRefRole.set_source_info()
        • VHDLXRefRole.target
        • VHDLXRefRole.text
        • VHDLXRefRole.title
        • VHDLXRefRole.update_title_and_target()
    • vhdl_parser module
      • pp()
      • Namespace
        • Namespace.__init__()
        • Namespace.clear()
        • Namespace.copy()
        • Namespace.fromkeys()
        • Namespace.get()
        • Namespace.items()
        • Namespace.keys()
        • Namespace.pop()
        • Namespace.popitem()
        • Namespace.setdefault()
        • Namespace.update()
        • Namespace.values()
      • VHDLParser
        • VHDLParser.__init__()
        • VHDLParser.add_label()
        • VHDLParser.analyze_entities()
        • VHDLParser.analyze_entity_interface()
        • VHDLParser.analyze_libraries()
        • VHDLParser.append()
        • VHDLParser.attrib
        • VHDLParser.clear()
        • VHDLParser.dedent()
        • VHDLParser.extend()
        • VHDLParser.find()
        • VHDLParser.findall()
        • VHDLParser.findallbetween()
        • VHDLParser.findindex()
        • VHDLParser.findsibling()
        • VHDLParser.findsubtext()
        • VHDLParser.findtext()
        • VHDLParser.findwithsubtext()
        • VHDLParser.findwithtext()
        • VHDLParser.get()
        • VHDLParser.get_comments()
        • VHDLParser.get_entity()
        • VHDLParser.get_file_with_entity()
        • VHDLParser.get_head_and_tail_comments()
        • VHDLParser.group()
        • VHDLParser.group_comments()
        • VHDLParser.index()
        • VHDLParser.insert()
        • VHDLParser.is_fence()
        • VHDLParser.items()
        • VHDLParser.iter()
        • VHDLParser.iterbetween()
        • VHDLParser.iterfind()
        • VHDLParser.itertext()
        • VHDLParser.keys()
        • VHDLParser.makeelement()
        • VHDLParser.move()
        • VHDLParser.move_header_comments()
        • VHDLParser.move_tail_comments()
        • VHDLParser.parse_file()
        • VHDLParser.pp()
        • VHDLParser.print_debug()
        • VHDLParser.remove()
        • VHDLParser.remove_comment_marks()
        • VHDLParser.replace()
        • VHDLParser.set()
        • VHDLParser.split_block_comments()
        • VHDLParser.subtext
        • VHDLParser.subtextbetween()
        • VHDLParser.tag
        • VHDLParser.tail
        • VHDLParser.text
        • VHDLParser.token_list_to_element_tree()
    • xelement module
      • XElement
        • XElement.__init__()
        • XElement.append()
        • XElement.attrib
        • XElement.clear()
        • XElement.extend()
        • XElement.find()
        • XElement.findall()
        • XElement.findallbetween()
        • XElement.findindex()
        • XElement.findsibling()
        • XElement.findsubtext()
        • XElement.findtext()
        • XElement.findwithsubtext()
        • XElement.findwithtext()
        • XElement.get()
        • XElement.group()
        • XElement.index()
        • XElement.insert()
        • XElement.items()
        • XElement.iter()
        • XElement.iterbetween()
        • XElement.iterfind()
        • XElement.itertext()
        • XElement.keys()
        • XElement.makeelement()
        • XElement.move()
        • XElement.pp()
        • XElement.remove()
        • XElement.set()
        • XElement.subtext
        • XElement.subtextbetween()
        • XElement.tag
        • XElement.tail
        • XElement.text
    • add_css_files()
    • add_nojekyll()
    • autodoc_process_docstring()
    • builder_inited()
    • doctree_resolved()
    • setup()

Indices and Tables

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